The present invention relates generally to lithographic processes for fabricating nanometer geometry electronic devices and more particularly to processes for fabricating high temperature superconducting material Josephson junctions.
The operation of Josephson junctions was initially depicted as a tunneling effect in superconducting materials in which a supercurrent flows between superconducting materials separated by a quantum barrier, such as a thin insulating film. Subsequently, the superconductive effect was observed with other quantum barriers (e.g. grain boundary junctions, point contact junctions as well as bridge junctions). To differentiate the latter quantum barrier junctions from the insulating film junctions, they are generally referred to as weak link junctions. Amongst the weak link junctions, bridge junctions can generally be differentiated from point contact and grain boundary junctions as being planar. Moreover, many weak link junctions, especially bridge junctions, can be characterized by current-voltage relations free from hysteresis due to their low capacitances. There are typically two modes of operation of a Josephson junction. In the zero-voltage mode, a supercurrent flows across the barrier or junction until it reaches a critical value (e.g. I.sub.c). In the non zero-voltage mode, current oscillations of a frequency proportional to the applied voltage occur and if irradiated with electromagnetic waves, current steps will appear at equal voltage intervals on a current-voltage display.
Unfortunately, the practical utility of Josephson junctions has been limited by the very low critical temperatures (T.sub.c) of many superconducting materials. With the discovery of high temperature superconducting (HTS) materials (T.sub.c &gt;77.degree. K.), interest has once again been renewed in Josephson junctions since such superconducting temperatures are more practically and commercially achievable. However, fabrication of Josephson junctions with HTS materials has proven to be extremely difficult because of their reactivity with most conventional dielectric materials and the high temperature deposition processes associated with such HTS materials. Moreover, one of the outstanding problems impeding the manufacture of superconducting electronics made from HTS materials is the inability of existing fabrication processes to provide accurate and reproducible positioning, orientation and density of such electronic devices. Typically, most existing HTS material Josephson junctions rely on the fabrication of grain boundary junctions. Unfortunately, the uniformity and manufacturing yield of such grain boundary processes is poor and positioning, as well as orientation and density of placement of such electronic devices is extremely limited. Moreover, such grain boundary junctions are extremely sensitive to minute changes in the deposition of the HTS material further reducing the yield of such processes.
The use of submicron geometries has been found useful for the high-frequency operation of Josephson junctions fabricated from HTS materials as a consequence of their resulting capacitances and density of placement of such devices. Matsui in U.S. Pat. No. 5,109,164 has described the length of the bridge as critical to the operation of weak link Josephson junctions. In particular, Matsui has indicated that the bridge length must be between 1 and 5.31 times the coherence length of the superconducting material wave function. Unfortunately, as the critical temperature (T.sub.c) of superconducting materials has increased, the coherence length for bridge-type Josephson junctions has decreased. This is especially pronounced in HTS materials. However, current fabrication techniques are inadequate to reproducibly achieve such dimensions. Recognizing such short coming, Matsui developed an alternative fabrication technique whereby accurate control of bridge length and width was not needed.
Several processes for the fabrication of Josephson junctions from HTS materials have been reported by Gross et al in Appl. Phys. Lett. 57, 727 (1990) and Char et al in Appl. Phys. Lett. 59, 733 (1991) and involve the engineered fabrication of grain boundaries as the quantum barrier. These techniques are not amenable to circuit fabrication because of the difficulty in controlling both the number and placement of the grain boundaries. The first grain boundary formation process uses custom SrTiO.sub.3 substrates made with two crystallographic orientations present. A HTS film grows following these orientations and a high angle, Josephson-like grain boundary forms at the interface. A refinement of this process uses a seed layer, deposited on the substrate, to form the basis for the other axis of growth. Another approach described by Daly et al in "Substrate Step-edge YBa.sub.2 Cu.sub.3 O.sub.7 of Squids," Appl. Phys. Lett. 58, 543 (1991) has been to form step-edge junctions by patterning the substrate prior to deposition of the superconducting thin film. Film growth on these substrates quite reproducibly forms a grain boundary at the etched step. While this technique is more controllable than the use of bi-crystalline substrates, it introduces additional processing that can degrade the surface of the starting substrate prior to deposition of the HTS material.
A more elaborate process for fabricating Josephson junctions described by Kern et al in J. Vac. Sci. Tech Bg, 2815 (1991) uses selective epitaxy on a substrate having a patterned silicon nitride overlayer. Electron beam lithography is used to pattern the silicon nitride film rather than the HTS material directly. Using this technique, bridges of HTS material down to 0.13 .mu.m have been formed but achieving finer resolution is limited by particulate formation during HTS deposition. Additionally, there are concerns about stress in the grown films and silicon outdiffusion from the silicon nitride mask. Electron beam lithography has also been used in combination with ion milling to pattern an HTS film directly for the fabrication of grain boundary junction. The minimum reported feature size obtained via this technique was 0.25 .mu.m, limited in part by the use of a thick, negative electron beam resist. Additionally, damage to the HTS film induced by the ion milling process can unacceptably degrade the HTS film characteristics as linewidths are reduced to 0.1 .mu.m and below.
Consequently, a need continues to exist for accurate and reproducible techniques to manufacture Josephson junctions employing HTS materials and having submicron dimensions. The present invention provides a novel direct-write electron beam lithography process in conjunction with a wet etch to reproducibly and accurately fabricate Josephson junction bridges of nanometer geometries.